1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same.
2. Related Art
There is available an FBC (floating body cell) memory device as a semiconductor memory device that is expected as a memory which replaces a DRAM. The FBC memory device has an N-type MOS transistor that has a floating body (hereinafter also referred to as a body region) on an SOI (silicon on insulator) substrate. The FBC memory device stores data “1” or data “0”, depending on the number of holes stored in the body region. For example, when the FBC is an n-type FET, the FBC memory device sets a state of the presence of many holes in the body region as the data “1”, and sets a state of the presence of few holes in the body region as the data “0”.
In recent years, there has been developed an FBC memory device that has an FBC formed on an SOI substrate and has a back gate electrode provided on a supporting substrate. A back bias is applied to the FBC memory device from the back gate electrode, thereby the floating body region is fully depleted. The FBC memory device can also increase a signal voltage from a memory cell by controlling the back bias.
In order to control the back bias, it is preferable that a BOX (buried oxidation) layer has a small film thickness, such as 25 nm or smaller. Furthermore, in order to increase the signal amount which is difference between data “0” and data “1”, it is preferable that the floating body region (a channel region), or an SOI layer, also has a small film thickness, such as 50 nm or smaller. However, the BOX layer usually has a film thickness of about 150 nm, and it is technically difficult to decrease the film thickness to 50 nm or below.
To solve the problem, a method of configuring the FBC with a FIN-type FET is considered. According to the FIN-type FET, gate electrodes can be provided at both sides of a fin. Therefore, the floating body can be fully depleted readily. The FIN-type FET does not require to be provided with a back gate electrode on the supporting substrate. Therefore, the BOX layer does not require a large film thickness.
However, when the FIN has a small thickness to sufficiently secure the signal amount, not only the floating body region but also source/drain regions have a small film thickness. When the source/drain regions have a small film thickness, a contact resistance in the source/drain regions becomes high. Impurity is usually implanted into the source/drain regions from above the FIN toward the upper surface of the FIN. In order to diffuse impurity in the total source/drain regions, annealing process is necessary for a long time or at a high temperature. This annealing process diffuses impurity in a channel region as well. Therefore, this has a problem of changing the characteristic of a memory cell (See T. Tanaka et al. “Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM” IEDM 04-919-04-923).